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Senior System Integration and Validation Engineer

NVIDIA· Engineer, ASIC
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Santa Clara, CA$168k - $264.5kfull-timePosted 1mo ago

About the role

Senior Engineer to lead system validation, debug, and cross-functional alignment on a flagship silicon program within NVIDIA's Silicon Co-Design Group. Focus on left-shifting validation coverage, AI-enabled validation workflows, and cross-stack debugging across silicon, board, firmware, and software boundaries.

Responsibilities

  • Own end-to-end system validation of NVIDIA GPU, SoC, and platform programs — feature checks, PVT stress, system-stress campaigns at scale, and multi-unit fleet testing.
  • Lead debug of the hardest cross-stack issues — logic, signal integrity, power delivery, firmware, and software interaction — and drive them to root cause with reusable workarounds and productized fixes.
  • Develop test plans, scripts, and automation for next-generation chips ahead of physical builds, translating architecture, boot flows, high-speed I/O, and power and thermal dependencies into executable coverage.
  • Design and deploy AI-enabled debug and validation workflows used by the team — with explicit guardrails (evals, regression validation, false-positive handling) and measurable impact on cycle time, debug velocity, or escape rate.
  • Translate complex silicon and system risk into decision-ready options for technical and executive audiences — without padding or hand-waving.
  • Partner with globally distributed teams across silicon design, DFT, firmware, software, manufacturing, and platform engineering — including counterpart engineers in India and other major hubs.
  • Lead crisis-mode debug task forces when a program is stuck, and convert the learnings into reusable methodology for adjacent programs.

Qualifications

  • BTech/BE or MTech/ME in Electronics, Electrical, or Computer Engineering (or equivalent experience)
  • 8+ years of post-silicon validation, system integration, or platform debug experience on shipped GPU, CPU, or SoC products
  • Hands-on debug depth across silicon, board, and software boundaries — logic design, signal integrity, power delivery, high-speed I/O, and PVT behavior
  • Strong EE fundamentals across SI/PI, power delivery, and thermal
  • Working understanding of GPU, CPU, or SoC architecture across PC, Datacenter, or Automotive
  • At least one example of resolving a multi-team failure to root-cause closure with a productized fix
  • Demonstrated AI-driven validation workflow with measurable impact and guardrails

Skills

Required:System validationDebug across silicon, board, and softwareAutomation and test planningAI-enabled validation workflows

Benefits

  • Competitive benefits
  • Flexible time off
  • Continuous learning
Last updated Sep 25, 2026. Interested? Apply on the company site.

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