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Senior Mask Layout Design Engineer

NVIDIA· Engineer, Mask Design
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Hybrid (Hsinchu), Hybrid (Taipei)full-timePosted 1mo ago

About the role

Senior mask layout design engineer responsible for physical layout of mixed-signal circuits (e.g., PLLs, high-speed I/O, ESD structures) in sub-micron CMOS using Cadence tools, collaborating with ASIC/mixed-signal engineers, including floor planning, custom layout, and design-rule/schematic verification.

Responsibilities

  • Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS technologies using Cadence tools.
  • Work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
  • Job duties will include floor planning, custom layout and verifying against design rules and schematics.

Qualifications

  • BSEE or equivalent experience
  • Minimum of 5+ years of relevant mask design / layout experience
  • Deep understanding of analog circuit layout concepts in submicron CMOS technologies; expert with Cadence custom circuit design tools - particularly virtuoso
  • Experience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre, Primeyield
  • Ability to communicate in spoken and written English; good teamwork and communication skills
  • Proficiency in scripting languages like perl, python, skill, etc.
  • Knowledge of DRC and LVS checking flows, ability to customize DRC and LVS decks.

Skills

Required:Analog circuit layoutCadence VirtuosoDRC/LVS toolingScriptingCommunication
Last updated Sep 11, 2026. Interested? Apply on the company site.

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