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ASIC Design and Verification Intern, SOC - 2027

NVIDIA· Intern
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ShanghaiinternPosted 1mo ago

About the role

ASIC Design and Verification Intern position in NVIDIA's SysASIC and Clock teams, focusing on RTL design and verification for SysASIC and clock-related IPs, with collaboration across multiple teams and opportunities to develop automation tools and AI-assisted flows.

Responsibilities

  • Participate in RTL design and verification of SysASIC and clock-related IPs
  • Develop and debug Verilog/SystemVerilog RTL, testbenches, assertions, and simulation regressions.
  • Analyze and resolve issues from simulation, formal verification, lint, CDC/RDC, synthesis, STA, and gate-level verification.
  • Collaborate with cross-functional teams to improve design quality, verification coverage, and development efficiency.
  • Develop scripts, automation tools and AI agent to improve design and verification flows.

Qualifications

  • Pursuing a BS/MS degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Understanding of digital logic design and front-end ASIC development flow, including RTL design, simulation, synthesis, STA, lint, and CDC/RDC.
  • Familiarity with clocking concepts, such as clock gating, clock-domain crossing, reset synchronization, PLLs, and timing fundamentals.
  • Proficiency in Verilog and/or SystemVerilog; knowledge of UVM, SVA, or functional coverage is a plus.
  • Familiarity with formal verification concepts and tools, including property specification, assertion-based verification (SVA), equivalence checking, or formal property verification.
  • Experience with Python, Perl, Tcl, shell scripting, C, or C++ is preferred.
  • Familiarity with Linux development environments and common EDA tools.
  • Strong analytical and debugging skills, attention to detail, and willingness to learn.
  • Good English communication skills and the ability to work effectively in a global team.

Skills

Required:Verilog
Nice to have:SystemVerilogUVM/SVA/functional coverageFormal verificationPython/Perl/Tcl/Shell/C/C++Linux and EDA tools
Last updated Sep 11, 2026. Interested? Apply on the company site.

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