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Senior Silicon Product Methodology Engineer

NVIDIA· Engineer, ASIC
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ShanghaiFull-timePosted 1mo ago

About the role

Senior role focused on defining and implementing validation and screening of new silicon features within high-volume manufacturing flows, translating product requirements into executable test methodologies, infrastructure, and production test plans to ensure quality, yield, and efficiency at scale. Cross-functional coordination to build DFP methodologies and ensure products meet SOL milestones with NVIDIA quality standards.

Responsibilities

  • Own end-to-end manufacturing methodology strategy, defining organization-wide standards adopted across teams, products, and future generations, and shaping how manufacturing issues are screened, debugged, and closed.
  • Translate system specs and product POR into DFP requirements, test content, coverage, flows, and testability requirements, and maintain the DFP roadmap across infrastructure planning, execution readiness, and sign-off alignment.
  • Partner multi-functionally to implement test content, debug hooks, and screening improvements, and drive alignment on manufacturability, test time, binning strategies, and cost-versus-coverage trade-offs.
  • Turn incomplete yield, coverage, and correlation issues into hypothesis trees, measurement plans, and executable paths to closure.
  • Define data and analytics frameworks to support yield analysis, anomaly detection, and continuous improvement.
  • Lead methodology strategy and DFP documentation as the single source of truth and feed findings into future methodologies, reusable methods, and production decisions.
  • Create production-standard test methods, analytics systems, and debug frameworks that become durable artifacts adopted by engineering teams across products and future generations.
  • Build secure, traceable, and validated AI-assisted workflows for analysis, debug, documentation, and methodology automation, with human oversight for critical engineering judgments.

Qualifications

  • BS/MS in Electrical Engineering, Computer Engineering, or related field (or equivalent experience)
  • 8+ years in silicon post-silicon validation and/or high-volume manufacturing test for complex SoCs, GPUs, CPUs, or similar
  • Hands-on experience with test content bring-up, limit setting, correlation to characterization, and yield/coverage optimization, and prior ownership of manufacturing test strategy from early planning through ramp to QS/production
  • Proficiency with scripting and data analysis (e.g., Python, MATLAB, R, SQL) for test data analytics, limit tuning, and yield/debug analysis
  • Demonstrated ability to frame ambiguous manufacturing problems, define evidence-driven trade-offs, and drive cross-functional alignment and closure around plans, dependencies, and sign-off criteria
  • Excellent communication skills and comfort authoring structured technical documents and test plans used by global manufacturing and validation teams
  • Strong AI-enabled skills and thinking, using AI to accelerate analysis, exploration, and documentation while maintaining rigor and measurable workflow impact
  • Prior ownership of manufacturing test strategy for a major silicon product (e.g., GPU/SoC/CPU) from early planning through ramp to QS/production
  • Track record creating reusable test methods, analytics frameworks, or debug tools adopted across teams, products, or programs

Skills

Required:Manufacturing test strategyTest content bring-upData analysis and scriptingCommunication and technical writing
Last updated Oct 16, 2026. Interested? Apply on the company site.

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