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Junior RTL Design Engineer, Google Cloud

Google· Google Cloud
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Hybrid (Tel Aviv, Israel; Haifa, Israel)Full-timePosted 1mo ago

About the role

Be part of a team developing custom silicon solutions powering Google's direct-to-consumer products. Contributes to ASIC SoC design from proof-of-concept to production, including RTL coding, microarchitecture definition, and design methodologies within the ML, Systems, & Cloud AI organization.

Responsibilities

  • Define the IP microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
  • Perform RTL development (coding and debug in Verilog, SystemVerilog).
  • Conduct function/performance simulation debug and Lint/CDC/FV/UPF checks.
  • Engage in synthesis, timing/power closure, and ASIC silicon bring-up.
  • Contribute to verification test plan and coverage analysis of block and SoC-level.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or System Verilog.
  • Experience in logic design and debug with Design Verification (DV).
  • Experience with microarchitecture and specifications.

Skills

Required:RTL designDesign verificationMicroarchitecture
Nice to have:Scripting (Python/Perl)SoC/ASIC knowledge

Benefits

  • Google is an equal opportunity employer and provides accommodation as needed; see EEO policy and belonging resources referenced in the job description.
Last updated Oct 23, 2026. Interested? Apply on the company site.

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