RTL Design Engineer, Google Cloud
RemoteFull-timePosted 1mo ago
About the role
Be part of a team developing custom silicon solutions powering Google’s direct-to-consumer products. Responsibilities include RTL/ASIC design from concept to production, IP microarchitecture, design flow, and collaboration across architecture, software, verification, power, timing, and test teams.
Responsibilities
- Define the IP microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
- Perform RTL development (coding and debug in Verilog, SystemVerilog).
- Conduct function/performance simulation debug and Lint/CDC/FV/UPF checks.
- Engage in synthesis, timing/power closure, and ASIC silicon bring-up.
- Contribute to verification test plan and coverage analysis of block and SoC-level.
Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 4 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
- Experience in logic design and debug with Design Verification (DV).
- Experience with microarchitecture and specifications.
Skills
Required:RTL designVerilog/SystemVerilogDesign verification (DV)
Nice to have:Scripting (Python or Perl)
Last updated Oct 23, 2026. Interested? Apply on the company site.
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