Senior Silicon Circuit Co-Design Engineer
NVIDIA· Engineer, ASIC
Santa Clara, CA$168k - $264.5kfull-timePosted 1mo ago
About the role
Senior engineer responsible for co-design, bring-up, and post-silicon validation of analog, digital, and mixed-signal circuits that underpin safety, security, reliability, and performance features, across the full PVT space, from first power-on through production sign-off.
Responsibilities
- Own the co-design, bring-up, and post-silicon validation of the analog, digital, and mixed-signal circuits that underpin NVIDIA's safety, security, reliability, and performance enhancement features — across the full PVT space, from first power-on through production sign-off.
- Close the simulation-to-silicon gap. Build methodologies that correlate measured circuit behavior against pre-silicon predictions, quantify divergences, and produce actionable analysis.
- Trace failures to their source and drive resolution through to confirmation.
- Own and build AI agents that automate test orchestration, data pipelines, and analysis flows to expand coverage and reduce cycle time.
- Build automation and analysis infrastructure to enable efficient multi-product execution without sacrificing depth or coverage.
- Contribute to decision-making tables; use data to drive binning, guard-band, and reliability sign-off decisions.
- Lead and mentor junior engineers and interns.
Qualifications
- BS or MS in Electrical Engineering, Computer Engineering, or equivalent lab experience
- 8+ years of hands-on silicon bring-up, frequency and power characterization, or post-silicon validation on real hardware
- Strong circuit fundamentals across analog, digital, and mixed-signal
- Hands-on lab depth with oscilloscopes, multimeters, DAQs, spectrum analyzers, and silicon debug tools; comfort with tester-to-system correlation
- Depth in product binning, PVT analysis, guard-banding, and optimization trade-offs; statistical fluency
- Exposure to critical path analysis, power integrity, dI/dt and PDN analysis, transistor physics, and silicon reliability aging mechanisms
- Scripting proficiency in Python, C/C++, or equivalent; able to build infrastructure for characterization
Skills
Required:Electrical engineering fundamentalsLab and measurementPVT analysis and guard-bandingPower integrity and PDN/dI/dt analysisScripting and automation
Benefits
- Equity
- Benefits package (as per company offerings)
Last updated Sep 25, 2026. Interested? Apply on the company site.
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