Senior Design Verification Engineer, Multimedia/AI/ML, Silicon
Mountain View, CA, USA$163k - $236kFull-timePosted 1mo ago
About the role
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
- Work with designers, architects, and other stakeholders to come up with detailed test plans, dependencies, and deliverables, while representing DV status throughout the development process.
- Plan the verification of multimedia design blocks at subsystem level by understanding the design specification, and interacting with architecture and design engineers to identify important verification scenarios.
- Work with architecture, software, design, and back-end implementation stakeholders to make technical decisions.
- Create and enhance constrained-random verification environments using system verilog and UVM. Identify and implement improvements to the verification methodologies.
- Identify verification gaps and demonstrate advancement towards tape-out through comprehensive coverage metrics. Debug tests with design engineers to deliver functionally correct design blocks.
Qualifications
- Bachelor's degree in electrical engineering or computer science, or equivalent practical experience.
- 8 years of experience with verification methodologies and languages (e.g., UVM and SystemVerilog).
- Experience with interconnect protocols (e.g., AXI, APB, ACE).
- Experience developing and maintaining verification testbenches, test cases, and test environments.
Skills
Required:verification methodologies (UVM, SystemVerilog)interconnect protocolstestbench development
Last updated Oct 23, 2026. Interested? Apply on the company site.
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