ASIC Design Verification Engineer, Digital Signal Processing
Remote$163k - $236kFull-timePosted 1mo ago
About the role
Role focused on shaping AI/ML hardware acceleration by driving verification for TPU technology, with emphasis on high-speed PHY DSP blocks, mixed-signal interfaces, and scalable UVM-based verification environments.
Responsibilities
- Verify RTL implementations against high-level architectural reference models (MATLAB, C++, or SystemC) using bit-exact and fixed-point verification methodologies.
- Verify the stability, tracking capability, and convergence of adaptive equalization loops (FFE, DFE) and timing recovery systems under varying channel impairments.
- Model and verify the functional interface between Digital DSP blocks and the Analog Front End (AFE) using Real Number Modeling (RNM) or SystemVerilog-AMS.
- Design, implement, and maintain scalable UVM-based simulation environments, SystemVerilog Assertions (SVA), and functional coverage metrics for digital signal processing blocks.
Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 8 years of experience in design verification (DV) with a focus on digital signal processing (DSP), communication systems, or arithmetic logic blocks.
- Experience with scripting in Python, Perl, or Makefile for automation.
Skills
Required:RTL verificationAdaptive equalization (FFE/DFE)SystemVerilog-AMS / RNMUVM
Nice to have:MATLAB/C++ reference models
Last updated Oct 23, 2026. Interested? Apply on the company site.
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