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Silicon Micro-architecture Design Lead, Google Cloud

Google· Google Cloud
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BengaluruFull-timePosted 1mo ago

About the role

Lead a team of engineers to design complex IPs/ subsystems for ASICs in data centers, driving micro-architecture innovation and coordinating multi-site teams to deliver high-performance, power-efficient accelerators.

Responsibilities

  • Lead a team of Engineers in the design organization to deliver complex IPs or Subsystems. Communicate and work with multi-disciplined and multi-site teams.
  • Define micro-architecture (uArch) specifications and block-level design documents, including interface protocols, block diagrams, transaction flows, and pipeline details.
  • Perform RTL development, subsystem integration, and SoC integration, as well as Lint, CDC, FV, and UPF checks.
  • Participate in simulation debug, synthesis, timing and power closure, and silicon bring-up.
  • Participate in test plan and coverage analysis of the block and SOC-level verification.

Qualifications

  • Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 10 years of experience in ASIC/SoC development with Verilog/SystemVerilog.
  • Experience in micro-architecture and design of IPs and Subsystems.
  • Experience in ASIC/SoC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Skills

Required:ASIC/SoC designVerilog/SystemVerilogmicro-architectureRTL developmentDFTcollaboration across teams
Last updated Oct 23, 2026. Interested? Apply on the company site.

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