Staff RTL IP/Component Design Engineer, Google Cloud
RemoteFull-timePosted 1mo ago
About the role
Advanced position at Google Cloud focusing on RTL IP/Component design for ASIC/SoC development, collaborating across architecture, software, verification, power, timing, and synthesis domains.
Responsibilities
- Define the block level design document such as interface protocol, block diagram, transaction flow and pipeline, etc.
- Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, and VHDL), function/performance simulation debug and Lint/CDC/FV/UPF checks.
- Support synthesis, timing/power closure, and FPGA/silicon bring-up.
- Participate in test plan and coverage analysis of the block and SOC-level verification.
- Communicate and work with multi-disciplined and multi-site teams.
Qualifications
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).
- Experience in ASIC development with Verilog/SystemVerilog, VHDL or Chisel.
- Experience with System on a Chip (SoC) development cycles.
Skills
Required:ASIC design verificationVerilog/SystemVerilogVHDLChisel
Last updated Oct 23, 2026. Interested? Apply on the company site.
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