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Memory Silicon Validation Engineer

NVIDIA· Engineer, ASIC
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Taipei, TaiwanFull-timePosted 4w ago

About the role

Senior Memory Qualification Engineer responsible for high-speed memory bring-up, characterization, and qualification on NVIDIA’s GPU, CPU, and SoC programs. Focus on root-cause analysis of memory marginality, development of AI-enabled qualification workflows, and cross-functional coordination with pre- and post-Si teams and external vendors.

Responsibilities

  • Bring up high-speed memory interfaces (GDDR, LPDDR, HBM) on complex GPU, CPU and SoC silicon — from first power-on through full PVT characterization and productization.
  • Own functional validation, IO tuning, timing margin analysis, and multi-vendor DRAM qualification across the memory controller, PHY, and DRAM device — for the full matrix of capacities, speeds, and configurations we ship.
  • Lead root-cause closure on the hardest multi-team memory failures — spanning silicon, controller, PHY, package, board SI/PI, firmware, and workload — with reusable workarounds and productized fixes.
  • Design and deploy AI-enabled workflows for margin data analysis, shmoo bucketing, failure signature detection, and workload-vs-margin correlation — with guardrails for trustworthy qualification decisions.
  • Partner with pre-Si architecture, design, and DV teams to translate memory features into post-Si validation plans, and feed post-Si learnings back into pre-Si methodology.
  • Work across globally distributed teams — silicon design, PHY, PCB, firmware, software, DRAM vendors, and manufacturing partners — including Taiwan and other hubs.

Qualifications

  • B.Tech or M.Tech in Electrical, Electronics, or Computer Engineering (or equivalent), plus 4+ years in the semiconductor industry with at least 3 years directly on memory interface bring-up, characterization, and qualification on shipped silicon.
  • Deep protocol and physical-layer understanding of GDDR, LPDDR, or HBM, including training, calibration, IO tuning, timing margin, and vendor-to-vendor behavior differences, with at least one concrete memory root-cause-to-fix example.
  • Strong hands-on lab fundamentals (oscilloscope, DMM, thermal chambers, protocol analyzers) and working knowledge of PCB stack-up, board layout, power planes, and SI/PI guidelines.
  • Demonstrated AI-driven workflow for memory characterization, margin analysis, or failure triage with measurable impact and adoption beyond the individual.

Skills

Required:Memory interface bring-up

Benefits

  • Competitive benefits
  • Flexible time off
  • Continuous learning
Last updated Sep 25, 2026. Interested? Apply on the company site.

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