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Senior Full Chip Layout Engineer

NVIDIA· Engineer, ASIC
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Yokneam, Israel, Tel Aviv, IsraelFull-timePosted 4w ago

About the role

NVIDIA is seeking a Senior Full Chip Layout Engineer to join the Networking Silicon engineering team, focusing on full-chip physical layout, convergence, and tape-out for high-speed communication devices. On-site roles in Israel (Yokneam or Tel Aviv).

Responsibilities

  • Perform physical layout for full-chip level, integration, pinning and bump route
  • Work with block owners and project managers to assure high quality convergence in all layout aspects
  • You will be responsible for chip layout from the floorplanning stage through tape-out

Qualifications

  • An Electronics Engineer certificate or a B.Sc. in Electrical Engineering
  • 5 years of hands-on Full-chip layout and Physical Verification experience
  • Strong background in Physical Verification methodologies, including DRC, LVS, ANT, ERC, and DFM for advanced process nodes
  • Knowledge in scripts' language: TCL, Unix and Shell
  • Experience in Linux environments
  • AI tools orientation or alternatively a desire to learn
  • Familiarity with physical build EDA tools, including Synopsys (ICC2/FC) and Cadence (Innovus)
  • Familiarity with Physical Verification tools: Synopsys (ICV), Siemens (Calibre)
  • Self-motivation, attention to detail and good interpersonal skills

Skills

Required:Full-chip layoutPhysical VerificationScriptingLinuxEDA ToolsPhysical Verification Tools
Nice to have:AI Tools Orientation
Last updated Sep 25, 2026. Interested? Apply on the company site.

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