ML Hardware Achitect
Hybrid (Tel Aviv, Israel; Haifa, Israel)Full-timePosted 4w ago
About the role
Lead the architectural definition and optimization of high-performance ML compute IP and acceleration blocks for Cloud AI silicon, shaping Google's TPU technology and AI infrastructure.
Responsibilities
- Lead the architectural definition, modeling, and specification of next-generation, high-performance ML compute IP and acceleration blocks for Cloud AI silicon.
- Own the ML IP architecture specification throughout the entire product lifecycle: concept exploration, cycle-accurate modeling, implementation, silicon bring-up, and production.
- Partner with AI research and algorithm teams (e.g., Google DeepMind, Gemini) and software compiler teams (XLA, PyTorch) to explore architectural trade-offs and define hardware requirements for emerging model architectures.
- Drive comprehensive architecture studies evaluating compute dataflows, numerical formats, sparsity, and specialized acceleration mechanisms such as key-value (KV) cache optimization.
- Drive performance, latency, power efficiency, and silicon area projections across model topologies and workload configurations.
Qualifications
- Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
- 15 years of experience in computer architecture, ML accelerator design, or high-performance processor architecture.
- Experience leading architectural definition and authoring architecture specifications for silicon or compute IP blocks.
- Experience with performance modeling, workload profiling, and hardware-software co-design.
Skills
Required:Architectural definitionPerformance modelingHardware-software co-design
Nice to have:Collaboration with research teams
Last updated Oct 23, 2026. Interested? Apply on the company site.
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