RTL Design Technical Lead, Networking, Google Cloud
Google· Server Chip Design team
Tel Aviv; HaifaFull-timePosted 4w ago
About the role
Be part of Google's Server Chip Design team, delivering custom silicon solutions for Google Cloud and consumer products. Lead RTL design and architecture efforts for networking ASICs from specification to production, collaborating across architecture, software, verification, power, timing, and synthesis to deliver high-quality SoC/RTL.
Responsibilities
- Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
- Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
- Participate in synthesis, timing/power, and FPGA/silicon bring-up.
- Participate in test plan and coverage analysis of the block and SOC-level verification.
- Communicate and work with multi-disciplined and multi-site teams.
Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 10 years of experience architecting networking ASICs from specification to production.
- 8 years of experience in technical leadership.
- Experience in one of the following areas: arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
- Experience developing RTL for ASIC subsystems.
Skills
Required:RTL designArchitecture definitionSynthesis and timing/power
Last updated Oct 23, 2026. Interested? Apply on the company site.
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