ASIC Power Manager, ML Accelerators
Sunnyvale, CA, USAPosted 4w ago
About the role
Power Design Manager within Google's silicon team overseeing power architecture, design and optimization for TPUs and AI/ML accelerators.
Responsibilities
- Manage a power design team responsible for power architecture, power optimization and system power integration.
- Lead an experienced team, define the processes, methods and tools to continuously improve the power efficiency of the TPU designs.
- Contribute to design power modeling and drive convergence to power targets.
- Investigate, specify, and deploy architectural and microarchitectural power optimization techniques, defining best practices and methodologies to achieve low-power RTL designs.
- Collaborate with cross-functional software and system teams to create novel power management architectures to meet power goals.
Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 10 years of experience with ASIC or SoC design.
- Experience with power design, power modeling, power architecture, or power reduction methodologies/techniques.
Skills
Required:Power designASIC/SoC design
Last updated Oct 23, 2026. Interested? Apply on the company site.
More open roles at Google
- Staff Network Security Engineer, Google Enterprise Network2d agoHybrid (Austin, TX; Sunnyvale, CA)
- Group Product Manager, Google Lens AI Shopping2d agoMountain View, CA, USA · Product Management
- UX Program Manager2d agoHybrid (New York, NY; San Bruno, CA) · UX Programs & Operations
- Senior Staff Software Engineer, Android Automotive OS2d agoHybrid (Kraków, Poland; Munich, Germany)
- 2d ago