Silicon Design Manager, RTL Machine Learning, Accelerator Design
Google· AI and Infrastructure team
Sunnyvale, CA, USA$192k - $278kFull-timePosted 4w ago
About the role
leads RTL design engineering for IP development focused on Compute Cores and TPU integration, with responsibilities spanning technical leadership, architecture collaboration, and cross-functional program governance in Google's AI/ML hardware acceleration efforts.
Responsibilities
- Lead, mentor, and manage a team of RTL Design Engineers performing tasks related to IP development for Compute Cores.
- Provide technical leadership to engineers and model best design practices (i.e., micro-architecture specifications, design reviews, code reviews, design methodology, etc.).
- Serve as the primary point of contact for all design-related activities on projects. Participate with Architecture and System Design teams in architecture definition, IP area estimation, power optimization, and performance enhancements.
- Collaborate closely with cross-functional teams (e.g., Verification, Design for Test, Physical Design, and Software) to make design plans and present project status throughout the development cycle.
- Drive improvements in design methodologies, processes, and quality control measures.
Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with Chip Design, ASIC Digital Design, and SystemVerilog.
- 8 years of experience in Computer Architecture and Register-Transfer Level.
- 3 years of experience in people management and developing employees.
Skills
Required:RTL DesignMicro-architectureArchitecture collaboration
Nice to have:Design for Testing (DFT)
Benefits
- Learn more about benefits at Google (see link in job description).
Last updated Oct 23, 2026. Interested? Apply on the company site.
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