Low Power Verification Engineer, Physical Design
Sunnyvale, CA, USA$163k - $236kFull-timePosted 4w ago
About the role
Role focused on shaping AI/ML hardware acceleration with emphasis on TPU architecture verification, post-layout low-power verification, and integration within Google’s TPU and AI/ML systems.
Responsibilities
- Design, deploy, and carry out post-layout low power verification methodologies according to execution schedules and tapeout signoff criteria to ensure successful multi-voltage implementation.
- Validate the implementation of complex multi-voltage design collateral, performing gate-level checks using industry-standard tools (e.g., Synopsys VCLP) to ensure power/ground integrity and Unified Power Format (UPF) alignment.
- Drive the resolution of complex Physical Design and Place & Route (P&R) anomalies, specifically mitigating issues such as wrong domain buffering, secondary power routing failures, and isolation clamping errors.
- Perform debugging on advanced Clock Tree Synthesis (CTS) implementations, analyzing tool behavior around level shifters in high fanout networks, duty cycle distortions, and multi-voltage skew management.
- Drive the continuous refinement of power state tables (PST) and Unified Power Format (UPF) scripts to ensure accurate translation from Golden RTL to the final physical netlist.
Qualifications
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
- 8 years of experience performing post-layout physical netlist validation and low-power signoff within advanced ASIC design workflows.
- Experience with static low-power rule-checking tools (such as VCLP or CLP), including experience in debugging structural checks and signal corruption issues.
- Experience validating special low-power components (isolation cells, power switches, level shifters, retention registers, and always-on cells) across all stages from synthesis to place and route.
Skills
Required:post-layout low power verificationUPF (Unified Power Format)static low-power rule-checkinggate-level checks
Nice to have:P&R (Place & Route) interactionCTS debugging
Last updated Oct 23, 2026. Interested? Apply on the company site.
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