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Physical Design Lead, ASIC

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Sunnyvale, CA, USA$192k - $278kPosted 4w ago

About the role

Lead role shaping AI/ML hardware acceleration with focus on TPU integration, responsible for custom datapath and matrix-multiplier blocks, from RTL to GDSII, within Google's AI/Infrastructure/TPU initiatives.

Responsibilities

  • Own critical custom datapath and matrix multiplication accumulator blocks, driving execution from RTL-to-GDSII including synthesis, floor-planning, place and route (PNR), timing closure, and physical signoff.
  • Understand math-intensive micro-architecture to perform detailed feasibility studies, analyzing performance, power, and area (PPA) tradeoffs to achieve optimal design closure.
  • Develop and improve advanced physical design methodologies and customize implementation recipes, specifically optimizing PPA across complex arithmetic pipeline structures. Manage different PNR tools - synopsys fusion compiler, cadence (Innovus/Genus), PrimeTime, StarRC, Calibre, Apache Redhawk.
  • Implement and execute key design phases: floor-planning, synthesis, placement, clock tree synthesis (CTS), timing closure, routing, extraction, physical verification (DRC/LVS, EM/IR), and final signoff.
  • Lead sub-chip execution and drive delivery, providing direct technical guidance and mentorship to a small team of engineers to ensure on-schedule project completion.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 10 years of experience in physical design, including custom structured datapath implementation.
  • Experience hardening dense compute units (dot-product engines, MACs, multipliers, ALUs) into high-frequency, low-power macros.
  • Experience in sub-7nm process nodes (FinFET and Gate-All-Around architectures), managing physical density and routing congestion typical of custom datapaths.

Skills

Required:Physical designRTL-to-GDSII flowFloorplanningPlace and route (PNR)Timing closureDRC/LVS/EM/IRLeadership/mentorship
Last updated Oct 23, 2026. Interested? Apply on the company site.

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