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DFT Engineer (RDSS Intern) - 2027

NVIDIA· Intern
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Hybrid (Taipei), Hybrid (Hsinchu)internPosted 3w ago

About the role

NVIDIA is seeking a DFT Engineer Intern in Taiwan (Taipei/Hsinchu) to verify custom IP macros, collaborate on verification strategies across IP/cluster/chip levels, optimize simulation flow with CAD, and generate test patterns for silicon bring-up.

Responsibilities

  • Verify our custom IP macros.
  • Collaborate with Design, Integration and TE teams to determine verification scope, develop strategies, implement test planning, and verify designs at IP level, cluster level, and full chip level
  • Collaborate with CAD team to optimize & smooth our simulation flow
  • Generating test patterns and perform silicon bring-up

Qualifications

  • Master degree of Electrical Engineering/Computer Engineering/Computer Science
  • Strong debugging and analytical skills with RTL/Gate-level design tracing (Verdi) and verification simulation tool (VCS)
  • Familiarity with SOC basic architecture (clock, reset, power rail, IO pad, package)
  • Understanding of Design for Testing including Scan/ATP G/BIST/JTAG is a plus
  • Skills of Python/Perl/Tck/C/C++ is a plus
  • Fluent English communication is required

Skills

Required:RTL/Gate-level design tracingVerification toolsSOC architecture
Nice to have:Programming languages
Last updated Oct 2, 2026. Interested? Apply on the company site.

About NVIDIA

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NVIDIA invents the GPU and drives advances in AI, HPC, gaming, creative design, autonomous vehicles, and robotics.

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