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Senior Package Layout Engineer

NVIDIA· Engineer, Sys Design
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full-timePosted 3w ago

About the role

Senior IC Packaging Design Engineer focused on delivering and designing high-speed interconnect systems for NVIDIA products, collaborating with multiple design teams to develop complex substrate layouts for ASIC packages, with emphasis on high-speed design, signal integrity, and PDN considerations.

Responsibilities

  • Collaborate to implement high speed and PDN design for ASIC packages.
  • Develop symbols, pad stack and perform substrate package routing, placement, stack-up, reference plane, power distribution using Cadence APD (Allegro) or SiP tools.
  • Optimize package pin out incorporating system level trade-offs of pins assignment.
  • Develop methodologies to improve layout environment, productivity, reliability, and schedule considerations.
  • In close cooperation with the SI/PI/HW design teams and product teams.
  • Planning, ensuring stakeholder management and leading projects from start to finish.

Qualifications

  • B.Sc. Electrical Engineering or an Electrical Practical Engineer certificate or equivalent experience
  • 5+ years hands-on in Package/PCB Layout and outing experience; including high speed design signal integrity practices
  • Experience in substrate layout of wire bond and flip chip packages, preferred
  • Knowledge in substrates or board manufacturing process
  • Significant background with Cadence Virtuoso and APD (Allegro) or SiP and/or other PCB layout tools

Skills

Required:High-speed PCB/Package LayoutSubstrate layout for wire bond and flip chipCadence APD (Allegro)Cadence VirtuosoSiP tools
Nice to have:Ansys/SIwave or Cadence Sigrity/PowerSI (optional, to stand out)Python/Perl/Shell scripting (basic parsing)

Benefits

  • Note: Benefits are not specified in the description.
Last updated Oct 2, 2026. Interested? Apply on the company site.

About NVIDIA

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NVIDIA invents the GPU and drives advances in AI, HPC, gaming, creative design, autonomous vehicles, and robotics.

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