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Senior Analog Layout Design Engineer

NVIDIA· Engineer, Mask Design
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Yokneam, Israelfull-timePosted 3w ago

About the role

Senior Analog Layout Design Engineer responsible for physical layout of high-speed mixed-signal circuits (PLL, high-speed I/O, SerDes, ESD structures) in sub-micron CMOS FinFET technologies using Cadence tools, collaborating with ASIC/mixed-signal teams, performing floor planning, custom layout, and verification.

Responsibilities

  • Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, SerDes, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS FinFET technologies using Cadence tools
  • Work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products
  • Floor planning, custom layout and verifying against design rules and schematics, EM/IR analysis

Qualifications

  • Minimum of 5 years of relevant mask analog layout experience
  • An Electronics Practical Engineer certificate or a B.Sc. in Electrical Engineering
  • Proven understanding of analog circuit layout concepts in submicron CMOS and FinFet technologies - such as Operational Amplifiers and ADC/DACs
  • Expert with Cadence custom circuit design tools - particularly Virtuoso
  • Experience running and debugging DRC and LVS with verification tools such as ICV, Calibre
  • Ability to work effectively in a team, good interpersonal skills, enthusiasm and positive energy

Skills

Required:Cadence VirtuosoDRC/LVS tooling (ICV, Calibre)Analog layout concepts (submicron CMOS, FinFET)
Nice to have:Scripting (Python)
Last updated Oct 2, 2026. Interested? Apply on the company site.

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