Senior Static Timing Engineer
Google· Chip Implementation / AI and Infrastructure
Sunnyvale, CA, USA$163k - $236kFull-timePosted 3w ago
About the role
Senior Static Timing Engineer on Google's chip implementation team, focusing on physical implementation of ASICs, timing closure, and development of static timing methodologies within high-performance compute devices and AI infrastructure.
Responsibilities
- Perform full chip static timing analysis, timing ECO creation for timing convergence, and final timing sign-off for ASIC tape outs.
- Debug and resolve common STA or design rule issues like unconstrained endpoints, maximum transition, minimum period, or minimum pulse width violations.
- Develop timing constraint and verify it for sign-off.
- Utilize Perl, Python, Tcl, or Bash to create static timing flow automation scripts.
- Own and maintain Primetime STA flows.
Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience with static timing analysis.
- Experience in Primetime or Tempus Tcl scripting and static timing analysis debug.
- Experience in full chip timing sign-off checklist criteria and overseeing final timing sign-off for ASICs.
- Preferred qualifications include: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science with emphasis on computer architecture; experience writing, reviewing and verifying complex Tcl constraints for static timing analysis; experience in extraction of design parameters, QoR metrics, and data trends; experience working with multiple foundries; knowledge of semiconductor device physics and transistor characteristics.
Skills
Required:Static Timing Analysis (STA)ScriptingTiming Sign-off
Benefits
- Learn more about benefits at Google (link provided in description)
Last updated Oct 23, 2026. Interested? Apply on the company site.
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