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Physical Design Technical Lead, ASIC, TPU

Google
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Sunnyvale, CA, USA$192k - $278kfull-timePosted 3w ago

About the role

Lead the physical design implementation and strategy for high-performance silicon (TPU), driving end-to-end execution from RTL to GDSII, coordinating with internal teams and external vendors, and ensuring optimal power, performance, and area.

Responsibilities

  • Lead the physical design implementation and strategy for high-performance silicon, with leadership scope ranging from critical, high-complexity subchips to overarching top-level execution based on project phases and team needs.
  • Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
  • Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
  • Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
  • Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.

Qualifications

  • - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • - 10 years of experience in physical design, including leading full-chip or sub-chip implementation such as RTL2GDSII and overseeing key stages like floorplanning, place and route, and timing closure for high-speed ASICs across various process nodes.
  • - Experience in Python, Tcl, or Perl scripting.

Skills

Required:Physical design leadershipRTL to GDSII design cycleScripting in Python/Tcl/Perl
Last updated Oct 23, 2026. Interested? Apply on the company site.

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