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Physical Design Lead, TPU, ASIC

Google
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Sunnyvale, CA, USA$192k - $278kFull-timePosted 3w ago

About the role

Lead the physical design implementation and strategy for high-performance silicon (TPU sub-chips), drive full design cycle from RTL to GDSII, and collaborate with internal teams and external vendors to optimize power, performance, and area for Google's TPU hardware.

Responsibilities

  • Lead the physical design implementation and strategy for high-performance silicon for critical, high-complexity subchips.
  • Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
  • Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal PPA results, including feasibility studies for new microarchitectures and RTL run optimization.
  • Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
  • Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling leadership to support project milestones.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
  • 10 years of experience in physical design, including leading full-chip or sub-chip implementation (RTL2GDSII) and managing floorplanning, place and route, and timing closure for high-speed ASICs across process nodes.
  • Experience in Python, Tcl, or Perl scripting.

Skills

Required:Physical design leadershipRTL to GDSII managementPPA optimizationScripting
Last updated Oct 23, 2026. Interested? Apply on the company site.

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