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TPU RTL Design Engineer, Google Cloud

Google· AI and Infrastructure / Google Cloud
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Sunnyvale, CA, USA$138k - $197kFull-timePosted 3w ago

About the role

SoC Design Engineer role focusing on RTL design for data center accelerators and TPU integration, collaborating cross-functionally to shape AI/ML hardware acceleration and deliver high-performance, power-conscious ASIC solutions.

Responsibilities

  • Work independently to create and review clock control subsystem's design micro-architecture specifications.
  • Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
  • Work with architecture and power teams to evaluate features and their impact.
  • Work with Design Validation (DV) teams to create test plans to verify and debug design RTL.
  • Work with physical design teams to ensure design meets physical requirements and timing closure.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 2 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development.
  • Experience in SystemVerilog for creating microarchitecture specifications and synthesizable RTL.
  • Experience using Python, Tcl, or Perl for automating design tasks and data analysis.
  • Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.

Skills

Required:Electrical engineering fundamentalsSystemVerilogPython, Tcl, or Perl

Benefits

  • Learn more about benefits at Google (link provided in job description).
Last updated Oct 23, 2026. Interested? Apply on the company site.

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