← All roles

SoC DFT Technical Manager, Google Cloud

Google· Google Cloud
Apply on company site
BengaluruFull-timePosted 3w ago

About the role

Leadership role defining and delivering DFT architecture for multi-core SoCs, focusing on TPU-related AI/ML hardware acceleration, with responsibilities spanning RTL planning to production release qualification and vendor/EDA tool leadership.

Responsibilities

  • Define and document the comprehensive DFT architecture for multi-core SoCs, including strategies for hierarchical scan compression, MBIST for huge memory instances, Functional BISTs, Analog components, Logic BIST, high-speed I/O loopback, and JTAG/IEEE 1149.1/1500/1687/1838 networks.
  • Lead the complete DFT lifecycle from RTL planning to pattern handoff, own the schedule, resource allocation, and milestone tracking to ensure zero-defect delivery.
  • Deploy next-generation DFT methodologies and automation flows to maximize test coverage, while minimizing test time, pattern count, and silicon area overhead.
  • Collaborate with post silicon team, Physical Design and Power Architects.
  • Support the post-silicon phase to achieve final Production Release Qualification (PRQ). Mentor senior technical staff, drive vendor EDA tool selection/qualification, and act as the primary technical liaison for DFT matters with stakeholders.

Qualifications

  • Bachelor's degree in Electrical, Computer Engineering or equivalent practical experience.
  • 10 years of experience in SoC DFT architecture and design.
  • 10 years of experience in DFT protocols including Scan Compression, MBIST, LBIST, JTAG (IEEE 1149.1), and iJTAG (IEEE 1687).
  • 10 years of experience with industry-standard EDA tools such as Siemens Tessent, Synopsys TestMAX/SMS, or Cadence Modus.
  • 4 years of people management experience developing employees and leading multiple SoC projects from RTL architecture through to post-silicon validation.
  • Experience in Tcl, Python, or Perl for developing automation flows.

Skills

Required:DFT architectureMBISTJTAG/IEEE 1149.1/1500/1687/1838EDA tools (Tessent, TestMAX/SMS, Cadence Modus)

Benefits

  • See Google Careers page for details.
Last updated Oct 23, 2026. Interested? Apply on the company site.

About Google

Google Search homepage

llmtext-to-speechvoice-ai-stack
Company profileWebsite

More open roles at Google