Senior Full-Chip RTL Integration Engineer
NVIDIA· Engineer, ASIC
Santa Clara, CA, Austin, TX$168k - $264.5k + equityfull-timePosted 2w ago
About the role
Responsible for integrating complex IPs and subsystems into large-scale SoCs, ensuring design quality, verification readiness, and DFT compliance. Collaborates with Architecture, Design, Verification, DFT, and Physical Design teams to deliver silicon products in a fast-paced environment.
Responsibilities
- Lead RTL integration of multiple internal and third-party IPs into complex ASIC/SoC designs, owning top-level connectivity, clocking, reset architecture, address mapping, and power domain integration.
- Work closely with Architecture, RTL Design, Verification, DFT, and Physical Design teams to drive system-level integration and design closure.
- Perform RTL quality checks including lint, CDC, RDC, synthesis, and connectivity validation.
- Develop and carry out integration-level verification plans using SystemVerilog/UVM, debug simulation failures, and support functional coverage closure.
- Collaborate with DFT teams to integrate scan, MBIST, LBIST, JTAG, and other test structures, and review ATPG reports and fault coverage metrics to ensure testability requirements are met.
- Support design signoff activities and ensure smooth handoff across implementation stages.
- Develop automation and scripting solutions to improve integration, verification, and debug productivity.
Qualifications
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field (or equivalent experience) with 8+ years of experience.
- Strong experience in ASIC/SoC RTL Integration.
- Excellent understanding of digital design fundamentals, SoC architecture, clocking, reset, and bus protocols.
- Strong verification knowledge with hands-on experience in SystemVerilog and UVM.
- Ability to independently verify block-level and integration-level designs.
- Strong understanding of DFT methodologies including Scan, ATPG, MBIST, LBIST, JTAG, and test compression techniques.
- Experience with lint, CDC, RDC, and design quality signoff flows.
- Strong debugging, analytical, and problem-solving skills.
- Good communication skills and ability to work effectively across multiple engineering teams.
Skills
Required:RTL IntegrationSystemVerilog/UVMDFT methodologiesLint/CDC/RDCDebugging and problem solvingCross-team collaboration
Nice to have:Automation/Scripting
Benefits
- equity
- comprehensive benefits package (per company offerings)
Last updated Oct 9, 2026. Interested? Apply on the company site.
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