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Senior Mask Layout Design Engineer

NVIDIA· Engineer, Mask Design
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Hybrid (Taiwan, Hsinchu), Hybrid (Taiwan, Taipei)full-timePosted 2w ago

About the role

Senior mask layout design engineer responsible for physical layout of mixed-signal functions (e.g., PLLs, high-speed SerDes, ADCs, ESD structures) in sub-micron CMOS technologies, collaborating with ASIC/mixed-signal teams, and performing floor planning, custom layout, and verification.

Responsibilities

  • Perform physical layout for mixed-signal functions like PLLs, high speed SerDes, Analog to Digital converters, ESD structures designs in groundbreaking sub-micron CMOS technologies using Cadence tools.
  • Work multi-functional with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
  • Take part in floor planning, custom layout and verifying against design rules and schematics.

Qualifications

  • BSEE or equivalent experience
  • Minimum of 5+ years validated experience in Mask and Layout Design
  • Deep understanding of analog circuit layout concepts in submicron CMOS technologies
  • Authority with Cadence custom circuit design tools - particularly virtuoso
  • Experience running and debugging with verification tools such as Dracula, Hercules, Calibre, and Primeyield
  • Ability to work successfully in a team, good interpersonal skills, passion and positive energy
  • Proficient in scripting languages like perl, python, skill etc.
  • Knowledge of DRC and LVS checking flows, ability to customize decks

Skills

Required:Analog circuit layoutCadence VirtuosoLayout verification toolsScriptingDRC/LVSTeam collaboration
Last updated Oct 9, 2026. Interested? Apply on the company site.

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