Senior Silicon Validation Methodology Engineer
NVIDIA· Engineer, ASIC
Shanghai, Chinafull-timePosted 2w ago
About the role
Senior level role focusing on definition, development, and execution of clocking and high-speed IO (PCIe, USB, MGBE, UFS, etc) functional validation methodology for NVIDIA's silicon across GPU/SoC/CPU, driving cross-functional collaboration, automation, and continuous improvement.
Responsibilities
- Own the definition and first-use of clocking and HSIO functional validation methodology from specification through silicon bring-up, covering functional, protocol, SI/PI, clocking behavior, system stability and integration test across corners and real bring-up conditions.
- Set the standard for validation so it is reused across a broad array of silicon products.
- Define what needs to be tested, why, and how — including coverage bounds, timing vs. power, signal integrity vs. performance, coverage vs. test time, milestone expectations, and signoff guidance — and turn that into executable concrete test content, pass/fail criteria, and bring-up plans.
- Drive cross-functional teams (architecture, design, board, FW, SW) collaboration to ensure robust methodology orchestration and alignment with validation design requirements, while also providing insights on trade-offs between coverage, schedule and effort.
- Drive continuous improvement in validation methodologies by creating and standardizing automated tools, scripts, and metrics that enhance efficiency and coverage in the validation workflow.
Qualifications
- A Master's or Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent experience.
- 8+ years of hands-on silicon validation methodology experience, with deep understanding of HSIO and Clocking architecture, design and validation including SerDes, protocol, functional and electrical validation, SI/PI, and power-aware trade-offs, in at least one of PCIe, CXL, USB, UFS, MGBE, or chip-to-chip / die-to-die interconnects.
- Demonstrated ability to set validation strategy under trade-offs such as functionality vs. power, signal integrity vs. performance, and coverage vs. test time, and to turn ambiguous specifications into executable tests.
- Expert debug of silicon HSIO and clocking issues, and the ability to deconstruct ambiguous failures into simpler, reusable validation and corrective approaches that raise quality and efficiency for the org.
- Strong collaboration skills and Proven track record of influencing and leading cross-functional/group (design, Board, FW, SW) consensus through product launches in low-power domains.
- Strong AI-enabled skills and thinking — use AI to accelerate analysis, exploration, and documentation while maintaining rigor, originality, and judgment that do not come from AI.
Skills
Required:Clocking and HSIO validationValidation strategy and test planningCross-functional leadershipDebug and issue deconstruction
Nice to have:AI-enabled analysis and documentation
Last updated Oct 9, 2026. Interested? Apply on the company site.
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