ASIC Verification Engineer - Clocks
NVIDIA· Engineer, Verification
Bengalurufull-timePosted 2w ago
About the role
Senior ASIC Verification engineer specializing in clocking and reset verification for NVIDIA Clocks Team, delivering high-quality clocking/reset logic across SOC automotive and datacenter ASICs with scalable verification across platforms.
Responsibilities
- Own validation of Clocking structures in Tegra automotive and datacenter products from start to finish, including test plan development, automation, validation flows development, coverage metrics, test execution, bug identification/fix and productization.
- Tackle sophisticated problems and develop a scalable solution that works across platform.
- Hands on industry-standard tools and state of the art verification methodologies, including System Verilog, UVM, C++, Perl, Python and NVIDIA custom compilers and tools.
- Partnering closely with clocks architecture and design team to validate clocks design.
- Coordinate with internal and external teams across time zones.
Qualifications
- BS or MS in EE/ECE or equivalent experience.
- 3+ years of relevant industry work experience.
- Good understanding of Logic Design and Architecture.
- Expertise in verification flows like SV constraint random verification, UVM, Formal Verification, Coverage metrics, profiling tools, X prop, etc.
- Exposure on block level and system-level verification.
- Strong coding skills in System Verilog, scripting languages (Perl/python) and C++.
- Ability to collaborate and work with multiple groups.
- Prior experience in implementing Test plans for pre-silicon platforms.
- Understanding of DFT/IST is optional.
Skills
Required:SystemVerilogUVMC++Python
Nice to have:Perl
Last updated Oct 9, 2026. Interested? Apply on the company site.
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