Senior Mask Layout Design Engineer
NVIDIA· Engineer, Mask Design
Santa Clara, CA, Austin, TX$132k - $207kfull-timePosted 2w ago
About the role
Senior mask layout design engineer responsible for physical layout of mixed-signal functions (PLL, high-speed I/O, ESD structures) in sub-micron CMOS using Cadence; collaborates with ASIC/mixed-signal teams for integration and verification.
Responsibilities
- Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general I/O's, ESD structures designs in innovative sub-micron CMOS technologies using Cadence tools
- Work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products
- Floor planning, custom layout and verifying against design rules and schematics
Qualifications
- Hold a BSEE or equivalent experience. MSEE is a plus
- 8+ years of relevant mask design / layout experience
- Tape-out experience with FinFET technology is required. Experience with TSMC N5/N4/N3 is preferred
- Experience with high-speed SerDes/RF layout design is helpful
- Experience with top level integration would be excellent to have
- Deep understanding of analog circuit layout concepts in submicron CMOS technologies
- Validated experience with Cadence custom circuit design tools - particularly virtuoso
- Experience running and debugging DRC and LVS with verification tools such as ICV/Calibre
- Ability to work optimally in a team, good interpersonal skills and positive energy
- Proficiency in scripting languages like perl, python, skill etc. is a plus
- Knowledge of DRC and LVS checking flows, ability to customize DRC and LVS decks
Skills
Required:Physical layoutCadence VirtuosoDRC/LVS debuggingFinFET tape-outAnalog layout
Nice to have:Scripting (Perl/Python)
Benefits
- equity
- benefits
Last updated Oct 9, 2026. Interested? Apply on the company site.
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