ASIC Physical Design Engineer
NVIDIA· Engineer, ASIC
Shanghai, Chinafull-timePosted 2w ago
About the role
ASIC-PD team hires both junior and senior engineers focusing on physical design from RTL to GSDII, including design quality checks, synthesis, formal checks, partitioning, constraints, timing analysis and signoff, with collaboration across ASIC/P&R/DFT/SI/ARCH to enable advanced processes and large-scale chips.
Responsibilities
- STA for hierarchical design.
- Constraints creation and validation, timing budget.
- Timing closure for both partition and full chip level.
- Special timing closure, such as io, test, clock etc.
- Synthesis, Netlist quality check, Formal Verification.
- Implement chip partition and floorplan.
- Function eco creation.
- Develop and enhance entire timing closure flow from frontend (pre-layout) to backend (post-layout).
- Flow automation development, Methodology in any of above areas.
Qualifications
- MS in EE, CS or Microelectronics with 1+ year experience is preferred
- Project experience in IC design implementation.
- Courses taken in circuit design, digital design
- Hand-on experience in EDA software from Synopsys (FC/DC/PT/Formality), Cadence (RC compiler/Genus/LEC) is helpful
- Proficient user of Python, perl or TCL is helpful
- Proficient in English reading and writing
Skills
Required:STAConstraintsTiming closureSynthesisFormal VerificationFloorplanning/Partition
Nice to have:Flow automationProgramming
Last updated Oct 9, 2026. Interested? Apply on the company site.
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