Senior DFT Methodology Engineer
NVIDIA· Engineer, ASIC
Santa Clara, CA$168k - $264.5kfull-timePosted 2w ago
About the role
Architect and develop test methodologies to make silicon testable, debuggable, and secure from bring-up; collaborate across timing, physical design, software, bring-up, and production to define and deploy DFT methodologies for next-generation products.
Responsibilities
- Own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, I1149.1, I1500, I1687, 1838, memory BIST, memory dump and DFX security methodology.
- Partner closely with timing, physical design, software, bring-up, and production teams to trade off cost and quality.
- Architect, develop and deploy DFT methodologies for next generation products including RTL design, Verification, pattern generation, partnering with timing, physical design, software, bringup, production.
- Mentor junior engineers on test designs and trade-offs including cost and quality.
Qualifications
- BS/MS Electrical or Computer Engineering (or equivalent experience) with proven DFT experience
- 10+ years of hands-on experience in SoC architecture, RTL design, and verification
- Strong analytical skills with experience using vendor tools to verify and validate test patterns and logic on highly complex, multi-million-gate designs
- Exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power
- Experience in Silicon debug and bring-up on the ATE with understanding of pattern formats, failure processing, and test program development
- Exceptional written and oral interpersonal skills with curiosity to work on rare challenges
Skills
Required:DFT methodologyRTL designPattern generationSilicon debug and bring-up
Nice to have:Programming / Scripting
Benefits
- equity
- comprehensive benefits
Last updated Oct 9, 2026. Interested? Apply on the company site.
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