Senior RTL Design Engineer, TPU
Google· AI and Infrastructure
Sunnyvale, CA, USA$163k - $236kFull-timePosted 2w ago
About the role
Role focused on SoC-level RTL design for data center accelerators, with emphasis on TPU architecture, management and control subsystems, and collaboration across software, system hardware, and validation teams to deliver production-grade RTL designs for Google’s TPU technology.
Responsibilities
- Work separately to create and review management and control subsystem's design microarchitecture specifications.
- Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
- Work with architecture and power teams to evaluate features and their impact.
- Work with design validation (DV) teams to create test plans to verify, and debug design RTL.
- Work with physical design teams to ensure design meets physical requirements and timing closure.
Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience in ASIC design.
- Experience with SystemVerilog/RTL coding.
- Experience with scripting languages (e.g., Tcl, Python or Perl).
Skills
Required:SystemVerilog/RTL codingASIC designScripting languages
Benefits
- Learn more about benefits at Google (provided link in job description)
Last updated Oct 23, 2026. Interested? Apply on the company site.
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