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Silicon SoC Design Verification Engineer, HSIO

Google
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Bengaluru, Karnataka, IndiaFull-timePosted 2w ago

About the role

High-Speed Input/Output (HSIO) Physical Layer (PHY) Verification Lead responsible for leading verification strategy and execution for HSIO interfaces in Google's next-generation custom silicon, collaborating across design, architecture, and post-silicon validation.

Responsibilities

  • Lead HSIO PHY integration verification at Sub-system and SoC levels.
  • Drive SoC-level test case development and port HSIO PHY IP-level test cases to the SoC environment.
  • Execute and oversee regressions in RTL, Gate-Level Simulations (GLS), and Timing simulations and perform HSIO PHY virtual tester (VT) simulations across RTL, GLS, and Timing environments.
  • Own testbench bring-up, including integration of third-party Verification IP (VIP). Generate EVCD and bench collaterals for target test cases to support downstream validation.
  • Perform deep waveform debugging and troubleshoot complex digital design and verification issues.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience
  • 8 years of experience in verification methodologies such as C, SystemVerilog and Open Verification Methodology/Universal Verification Methodology (OVM/UVM)-based constrained random verification.
  • Experience of high-speed protocols including USB2/USB3, PCIe, UFS, MIPI, and in loopback test concepts.
  • Experience with HSIO PHY Controllers and PHY+ controller test case porting.

Skills

Required:CSystemVerilogOVM/UVMRTL/GLS/Timing simulationstestbench bring-upwaveform debugging
Last updated Oct 23, 2026. Interested? Apply on the company site.

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