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SoC DFT Engineer, Cloud

Google· AI/ML Hardware - DFT and Test
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Sunnyvale, CA$163k - $236kFull-timePosted 2w ago

About the role

Engage in defining and implementing advanced Design-for-Test (DFT) methodologies for Tensor Processing Units (TPUs) and related IPs within Google's AI/ML hardware initiative. Focus on DFT strategy, verification, and integration of test features across highly digital SoCs, with emphasis on TPU architecture and production-quality test efficiency.

Responsibilities

  • Develop and document DFT strategy, architecture and test sequences, including hierarchical DFT, MBIST, ATPG and I/JTAG, and associated boot up and execution sequences.
  • Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high test quality.
  • Develop diagnostic databases, software and hardware for logic and memory fail debug.
  • Design and implement system level test strategy.
  • Implement core DFT circuitry, including insertion and hook-up of scan chains, DFT compression, Logic BIST, TAP controllers, and Memory BIST (MBIST) logic for IP blocks.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 5 years of experience in DFT architecture, implementation, and verification for SoCs.
  • Experience in silicon bring-up, debug, or validation of DFT features.
  • Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT).

Skills

Required:DFT architectureMBISTJTAG/iJTAGATPGsilicon bring-up and debug

Benefits

  • Learn more about benefits at Google (external link)
Last updated Oct 23, 2026. Interested? Apply on the company site.

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