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Senior Test Engineer, CMOS Backplane, Raxium

Google· Google (Raxium)
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Fremont, CA, USA$159k - $230kFull-timePosted 2w ago

About the role

Senior Test Engineer responsible for developing CMOS backplane test solutions for microLED display panels, coordinating with CMOS/panel test teams, and contributing to production and R&D test frameworks in Google's Raxium display group.

Responsibilities

  • Develop, validate, optimize standards and engineering CMOS Backplane test solutions for microLED display panels, including CMOS control software solutions. Ensure software test platform and architecture meet the needs of fast moving production and R&D environments.
  • Interface with wafer-level probe cards, test equipment, and instrumentation to facilitate CMOS/Silicon testing and characterization.
  • Identify, diagnose, resolve electrical issues during wafer-level testing using digital oscilloscopes and other testing equipment.
  • Collaborate with CMOS and panel test engineering teams to define and implement high-speed, automated testing solutions for IC/Silicon/CMOS and microLED displays, and debug process plans for manufacturing.
  • Work with the Test Engineering team to enhance and develop test frameworks based on requirements from the Reliability Team.

Qualifications

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized field (e.g., Optics, Sensors, Audio/DSP, etc.), or equivalent practical experience.
  • 4 years of experience with Silicon, CMOS, and IC test development.
  • 3 years of experience with Silicon test hardware, software debugging, and data analysis in a Research and Development (R&D) or manufacturing environment.

Skills

Required:CMOS backplane testingTest software developmentDebugging and data analysis

Benefits

  • Learn more about benefits at Google (linked in job description).
Last updated Oct 23, 2026. Interested? Apply on the company site.

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