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ASIC Design Verification Manager, TPU Compute

Google· AI and Infrastructure
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Sunnyvale, CA, USA$192k - $278kFull-timePosted 2w ago

About the role

Lead a functional verification team for Google’s TPU Compute initiatives, driving verification strategy and infrastructure across subchip, subsystem, and full-chip levels, with collaboration across design, architecture, and power teams to ensure architectural compliance and performance goals.

Responsibilities

  • Lead the functional verification team for significant portions of TPU Compute, setting priorities, coaching, and developing advanced verification infrastructure (subchip, subsystem, fullchip)
  • Define and drive comprehensive verification strategies for complex compute subsystems in collaboration with design, architecture, and power teams
  • Architect scalable, reusable verification environments and flows, adopting industry-leading methodologies to improve efficiency
  • Provide technical leadership and mentorship to junior engineers, conduct code reviews, and establish verification quality standards
  • Partner with architects and design leads to influence micro-architectural decisions to improve verification throughput and overall quality

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience
  • 10 years of experience with verification, SystemVerilog, and UVM
  • 3 years of experience in people management

Skills

Required:VerificationSystemVerilogUVM

Benefits

  • Learn more about benefits at Google (provided link in job description)
Last updated Oct 23, 2026. Interested? Apply on the company site.

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