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ASIC Design Verification Technical Lead, High-Speed DSP

Google· AI and Infrastructure
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Hybrid (Sunnyvale, CA; Haifa, Israel; Tel Aviv, Israel)$240k - $333kFull-timePosted 2w ago

About the role

Lead design verification for high-speed DSP blocks and TPU-related architectures, shaping verification methodologies and driving emulation and post-silicon correlation for Google's AI hardware accelerators.

Responsibilities

  • Design, build, and scale constrained-random verification environments using SystemVerilog and UVM for high-speed physical-layer DSP blocks.
  • Build co-simulation frameworks and predictors to compare RTL implementation output against high-level algorithmic models.
  • Define and execute functional coverage plans, utilizing covergroups and SystemVerilog Assertions to verify architectural corner cases, fixed-point quantization effects, and numerical overflows.
  • Author dynamic stimulus sequences and virtual sequencers to stress-test adaptive feedback loops under realistic channel impairments, including noise, ISI, and high-frequency jitter profiles.
  • Lead the debugging of RTL and environment failures, collaborating closely with algorithm and DSP designers to isolate and resolve discrepancies between the RTL implementation and the specification.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
  • 12 years of experience in design verification.
  • Experience in high-speed PHY layers, high-speed interface subsystems, or mixed-signal verification.

Skills

Required:SystemVerilogUVM (Universal Verification Methodology)Constrained-random verificationRTL verification
Nice to have:Digital design and DSP

Benefits

  • US: $240000 - $333000 (USD) + 25% bonus target + equity + benefits
Last updated Oct 23, 2026. Interested? Apply on the company site.

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