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Senior Silicon Design Verification Engineer, Google Cloud

Google
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Bengaluru, Karnataka, IndiaFull-timePosted 2w ago

About the role

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. Own the full verification life-cycle for AI/ML workloads on TPU hardware, build constrained-random verification environments, and collaborate across design and verification teams to meet stringent AI/ML performance and accuracy goals.

Responsibilities

  • Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
  • Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology. Verify designs with SystemVerilog Assertions and industry leading formal tools.
  • Identify and write all types of coverage measures for stimulus and corner-cases.
  • Debug tests with design engineers to deliver functionally correct design blocks.
  • Close coverage measures to identify verification holes and to show progress towards tape-out.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 8 years of experience in verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
  • Experience in verification and debug of IP/subsystem/SoCs in the networking domain such as packet processing, bandwidth management, congestion control.
  • Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).

Skills

Required:SystemVerilogSpecman/E languageConstrained-random verificationSystemVerilog Assertions
Nice to have:Formal verification tools
Last updated Oct 23, 2026. Interested? Apply on the company site.

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