SRAM Design Engineer
NVIDIA· Engineer, ASIC
Santa Clara, CA$116k - $189.8kfull-timePosted 1w ago
About the role
NVIDIA is hiring an SRAM Design Engineer to contribute to embedded SRAM design and SRAM compiler development within the Digital IP group, collaborating with SOC design, silicon test, and productization teams to deliver high-performance, area-efficient SRAM solutions for NVIDIA chips.
Responsibilities
- Embedded SRAM design: Transistor-level circuit design, supervising layout implementation, physical and logical verification, and debug of SRAM macros.
- SRAM compiler development: Envisioning, defining, and coding more efficient ways to automate the simultaneous assembly and validation of multiple unique SRAM macros using NVIDIA's extensive compute resources.
- Advanced development: Exploring the potential of future process nodes and developing techniques to realize optimal power, performance, and area characteristics.
- Guiding SOC design, silicon test, and productization efforts: Collaborate with SOC design partners to help them achieve their overall performance and cost goals, guide the silicon test and characterization efforts, and working with productization teams to prepare new silicon for the demanding requirements of real-world applications.
Qualifications
- BSEE minimum (or equivalent experience), MSEE or PhD
- 2+ years of professional experience in SRAM design
- Familiarity with Cadence Virtuoso schematic and layout capture tools
- Willingness and ability to use AI effectively in day-to-day tasks
Skills
Required:Embedded SRAM designCadence VirtuosoAI tools usage
Nice to have:SRAM compiler development
Benefits
- equity
- benefits (see NVIDIA benefits page)
Last updated Oct 16, 2026. Interested? Apply on the company site.
About NVIDIA
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