← All roles

Senior Circuit Timing Engineer

NVIDIA· Engineer, ASIC
Apply on company site
Hybrid (Santa Clara, CA), Remote$168k - $264.5kfull-timePosted 1w ago

About the role

Senior circuit timing engineer role focusing on timing analysis, signoff, and timing model development for custom macros in deep submicron technologies, with collaboration across PD, DFX, Clocks and other teams.

Responsibilities

  • Participate in ground breaking processor design in deep submicron technologies.
  • Work as part of a global circuits team to design innovative circuits for hardware security, adaptive clocking, and power management solutions.
  • Drive timing analysis and signoff of custom circuit macros (digital, semi-custom and analog mixed-signal).
  • Validate timing of custom circuit designs using STA tools including Nanotime, PrimeTime, Tempus and various SPICE simulation tools.
  • Collaborate with cross-functional teams to improve the power, performance, area and reliability of NVIDIA's next generation products through custom circuit solutions and detailed transistor-level analysis.
  • Develop timing models and methodology for innovative and unique custom macro designs.
  • Transistor-level circuit design and timing, schematic entry, and layout delivery.
  • Integrate AI/ML techniques directly into the design process and methodology.
  • Work with PD, DFX, Clocks, and other teams on timing signoff strategy, timing constraints, timing and power convergence, DFT, as well as timing ECO implementation.

Qualifications

  • BSEE/MS preferred in Electrical, Computer Engineering or equivalent experience.
  • 6+ years of digital circuit design experience for Masters and 8+ years for Bachelors.
  • Excellent understanding of deep submicron process issues and digital circuit design techniques.
  • Expertise and in-depth knowledge of industry standard STA tools such as Nanotime, Primetime, Tempus, and other timing analysis tools.
  • Hands on experience running Spice simulations, EM/IR analysis, and static timing analysis/closure.
  • Proven experience in timing constraints generation and management.
  • Hands on experience in design and analysis of low power circuits (power gating, decaps, multi-vt, etc..) is a plus.
  • Expertise in analysis and fixing of timing paths through ECOs including crosstalk and glitch noise.
  • Solid understanding of extracted timing models and the usage of .libs in Primetime.
  • Knowledge of process variation effect modeling and experience in design convergence in multi GHz deep submicron technology.

Skills

Required:Timing analysisSPICE simulationsDigital circuit design
Nice to have:Low power design

Benefits

  • Equity
  • Benefits (referenced in posting)
Last updated Oct 16, 2026. Interested? Apply on the company site.

About NVIDIA

World Leader in AI Computing

NVIDIA invents the GPU and drives advances in AI, HPC, gaming, creative design, autonomous vehicles, and robotics.

AIautonomous vehiclesgaminggpugraphics cardhigh performance computingliquid-ai-recruiting-targetllm
Company profileWebsite

More open roles at NVIDIA