Senior ASIC Design Engineer - Memory Subsystem
NVIDIA· Engineer, ASIC
Santa Clara, CA$136k - $218.5kfull-timePosted 1w ago
About the role
Senior ASIC Design Engineer to join NVIDIA's Memory Subsystem Team, collaborating across architects, verification, formal verification, and physical design to deliver high-performance interconnects, memory controllers, and accelerators for NVIDIA SoCs.
Responsibilities
- Collaborate with architects/design verification/formal verification/physical design teams to deliver a world-class memory subsystem solution (SOC interconnects, ordering controllers, memory accelerators).
- Responsible for micro-architecture and design including RTL design, synthesis and timing analysis using CAD tools and latest process technologies.
Qualifications
- BS or MS in Electrical Engineering or Computer Engineering or related degree (or equivalent experience)
- 5+ years of experience
- Strong proficiency of Verilog or VHDL
- Scripting language like PERL
Skills
Required:Verilog or VHDLScripting (Perl)
Nice to have:High-speed coherent interconnects (CHI/CXL/PCI-E)Multiple clock domains and asynchronous interfacesHardware-managed coherency and system-level caches
Benefits
- equity
- benefits (see company benefits page)
Last updated Oct 16, 2026. Interested? Apply on the company site.
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