Senior ASIC Design Verification Engineer, Cloud
Sunnyvale, CA, USA$163k - $236kFull-timePosted 1w ago
About the role
Role focused on verifying complex digital designs for Google Cloud TPUs and data-center accelerators, with responsibilities spanning planning, development of constrained-random verification environments, coverage analysis, and silicon bring-up.
Responsibilities
- Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience with design verification.
- Experience in verifying digital logic at RTL using SystemVerilog/UVM for ASICs.
Skills
Required:SystemVerilog/UVMDigital logic verificationConstrained-random verification
Last updated Oct 23, 2026. Interested? Apply on the company site.
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