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Senior Technical Program Manager, Chip DevOps and Methodology

Google· Unknown
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Hybrid (Tel Aviv; Haifa)UnknownPosted 1w ago

About the role

Technical Program Manager focused on delivering a unified silicon design methodology, overseeing EDA toolchains, and optimizing cloud compute and automation workflows for hardware design pipelines.

Responsibilities

  • Manage programs the definition, standardization, and company-wide adoption of a unified design and verification methodology. Drive alignment on consistent coding standards, automated checks, Process Design Kits (PDK) management, and IP reuse protocols.
  • Define, manage, and deliver complex infrastructure and CAD roadmaps, ensuring projects are completed on time, within budget, and with minimal disruption to design timelines.
  • Manage programs the deployment, licensing, and scaling of EDA tools (e.g., Synopsys, Cadence, Siemens) across hybrid or fully cloud-based environments, ensuring tool flows strictly adhere to the unified methodology.
  • Lead initiatives to optimize compute infrastructure (e.g., high-performance computing clusters, storage, and cloud instances) to manage massive simulation, synthesis, and physical design workloads.
  • Drive the strategy and implementation of automated workflows, continuous integration, and continuous verification (CI/CD) pipelines.

Qualifications

  • Bachelor's degree in Engineering, Computer Science, or equivalent practical experience.
  • 8 years of experience as a technical program manager or engineering lead.
  • Experience in supporting unified design/verification methodologies (e.g., standardized UVM frameworks, unified linting/CDC rules, automated regression tracking) or experience with software engineering lifecycle management or Site Reliability Engineering (SRE) principles.
  • Experience with the front-to-back silicon design lifecycle (e.g., RTL design, verification, synthesis, STA, place and route, tape-out) or experience in building automation, CI/CD pipelines, and Infrastructure as Code (IaC) environments for engineering workflows.

Skills

Required:Unified design/verification methodologyEDA tooling and workflowsCI/CD for hardware workflows
Last updated Oct 23, 2026. Interested? Apply on the company site.

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