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SoC Power Architect, Devices and Services, Silicon

Google· Hardware / SoC / Devices and Services
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Mountain View, CA, USAFull-timePosted 1w ago

About the role

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. Responsible for defining power requirements and driving cross-functional power optimizations for Tensor mobile SoCs, with emphasis on Power-Performance-Area (PPA) under peak current and thermal constraints.

Responsibilities

  • Lead the definition of power requirements for Tensor mobile SoCs to optimize Power-Performance-Area (PPA) under peak current and thermal constraints.
  • Own and drive cross-functional teams to deliver on competitive power key performance indicators (KPIs) for one or more major SoC IPs such as memory subsystem, multimedia subsystem, etc.
  • Propose and drive power optimizations throughout the design process from concept to mass productization.
  • Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions.
  • Represent the status of SoC power to executive leadership team.

Qualifications

  • Bachelor's degree in Electrical Engineering or equivalent practical experience.
  • 10 years of experience in power management or low power design/methodology.
  • Experience with low power architecture and power optimization techniques (multi Vth/power/voltage domain design, clock gating, power gating, DVFS, AVS).
  • Experience with full product delivery cycle (definition, architecture, design and implementation, testing, productization).

Skills

Required:Power managementLow power architectureDVFS / AVSClock gating / power gatingCross-functional leadership

Benefits

  • Learn more about benefits at Google (link provided in description).
Last updated Oct 23, 2026. Interested? Apply on the company site.

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