← All roles

Design Verification Engineer, Silicon Engineering

Google· Silicon Engineering
Apply on company site
Bengaluru, Karnataka, IndiaFull-timePosted 1w ago

About the role

Be part of a team that pushes boundaries, developing custom silicon solutions powering Google's direct-to-consumer products. Verify next-generation custom silicon accelerators and SoCs, build advanced UVM test environments, and collaborate across design, architecture, and emulation teams to deliver production-quality silicon.

Responsibilities

  • Create and improve constrained-random verification environments using SystemVerilog and UVM. Use SystemVerilog Assertions (SVA) and formal tools for formal verification.
  • Perform power-aware simulations and formal verification to validate power management features like clock gating, power gating, and Dynamic Voltage and Frequency Scaling (DVFS). Develop and implement power-aware test cases, including stress and corner-case scenarios, for robust power integrity.
  • Develop and execute coverage-driven verification plans to ensure comprehensive coverage of ASIC designs. Collaborate with design engineers to resolve coverage issues and improve design quality.
  • Plan the verification of complex digital design blocks by understanding design specifications and collaborating with design engineers to identify key verification scenarios.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 4 years of experience verifying digital logic at RTL using System Verilog for FPGAs and ASICs.
  • Experience with UVM Testbenches/environments.

Skills

Required:SystemVerilogUVM (Universal Verification Methodology)SystemVerilog Assertions (SVA)
Last updated Oct 23, 2026. Interested? Apply on the company site.

About Google

Google Search homepage

llmtext-to-speechvoice-ai-stack
Company profileWebsite

More open roles at Google