Senior Edge-AI SoC Design Verification Engineer
RemoteFull-timePosted 1w ago
About the role
Be part of a team developing custom silicon solutions powering Google's direct-to-consumer products. Build verification components, constrained-random testing, system testing, and drive verification closure for digital designs in Google Cloud hardware initiatives.
Responsibilities
- Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
- Identify and write all types of coverage measures for corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
Qualifications
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 8 years of experience with creating and using verification components and environments in standard verification methodology.
- Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Skills
Required:SystemVerilogUVM (Universal Verification Methodology)Constrained-random verificationDebugging
Nice to have:Formal verification
Last updated Oct 23, 2026. Interested? Apply on the company site.
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