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ASIC Electrical Analysis and Convergence Engineer, Silicon Engineering

Google· Silicon Engineering
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BengaluruFull-timePosted 1w ago

About the role

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You will own block or subsystem signoff for complex logic blocks and work closely with Physical Design collaterals to ensure high-quality silicon meets functional, manufacturing, and PPA requirements for subsystems.

Responsibilities

  • Drive PG (Power and Ground) bump assignments, Redistribution Layer (RDL) routing, IR (Static, Dynamic), EM and Inrush convergence for multiple IPs using industry-standard analysis tools (RedHawk-SC, Voltus, SPICE, etc.)
  • Lead Electrostatic Discharge (ESD) convergence for low-to-mid complexity Google IPs utilizing basic ESD concepts and DEF-based tools (Pathfinder-Classic, Pathfinder-SC, etc.)
  • Suggest basic to moderate complexity changes for PG Grid, flows, and methodologies. Partner with internal experts, technology teams, CAD, and EDA partners to address tool enhancements, bugs, and workarounds.
  • Write moderate complexity code/scripts to accelerate convergence, streamline debug, and perform deep-dive analysis.
  • Guide junior engineers and interns to achieve convergence across multiple IPs and methodology initiatives.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 4 years of experience in Power Delivery Network(PDN) convergence (IP/SOC level), CAD/EDA tool support, or PDN methodology.

Skills

Required:Power Delivery Network (PDN) convergenceIR (Static, Dynamic)EM (Electromigration) and Inrush analysis
Nice to have:ESD convergence
Last updated Oct 23, 2026. Interested? Apply on the company site.

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